Publications (CASLAB)

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Journal Papers

  • N. Aras and A. Yurdakul, “A New Multi-objective Mathematical Model for the High-level Synthesis of Integrated Circuits,” Applied Mathematical Modelling, Volume 40, Issue 3, pp. 2274-2290, 1 February 2016.
  • G. A. Malazgirt, A. Yurdakul and S. Niar, “Customizing VLIW Processors from Dynamically Profiled Execution Traces”, Microprocessors and Microsystems: Embedded Hardware Design, vol. 39, no. 8, pp. 656–673, November 2015.
  • S. Bayar and A. Yurdakul, “PFMAP: Exploitation of Particle Filters for Network-on-chip Mapping,” IEEE Transactions on VLSI Design, vol. 23, no. 10, pp. 2116 - 2127, October 2015.
  • E. Deniz, A. Sen, B. Kahne, J. Holt, MINIME: Pattern-Aware Multicore Benchmark Synthesizer, IEEE Transactions on Computers, 2014. PDF
  • Marcelo Sousa, and Alper Sen, LLVMVF: A Generic Approach for Verification of Multicore Software, Journal of Electronic Testing: Theory and Applications, 2013. PDF
  • E. Deniz, A. Şen, and J. Holt, "Verification and Coverage of Message Passing Multicore Applications, " ACM Transactions on Design Automation of Electronic Systems, 2012
  • D. Fennibay, A. Yurdakul, and A. Şen, "A Heterogeneous Simulation and Modeling Framework for Automation Systems, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012
  • S. Bayar and A. Yurdakul, “A Dynamically Reconfigurable Communication Architecture For Multicore Embedded Systems,” Journal of Systems Architecture,Volume 58, Issues 3–4, Pages 140–159, March 2012.
  • A. Şen, Concurrency-Oriented Verification and Coverage of System Level Designs, ACM Transactions on Design Automation of Electronic Systems, accepted, 2011.
  • A. Şen, B. Akşanlı, and M. Bozkurt, Speeding-up Cycle Based Logic Simulation using Graphics Processing Units , International Journal of Parallel Programming, DOI: 10.1007/s10766-011-0164-7, 2011.
  • A. Yurdakul, B. Kurumahmut, G Kabukcu, “Generic Model for Application-Specific Processors on Reconfigurable Fabric,” in Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s, Vol. 63, August 2010.
  • S. Little, D. Walter, K. Jones, C. J. Myers, and A. Şen, "Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces, " International Journal of Foundations of Computer Science (IJFCS), vol. 21, Iss. 2, pp. 191-210, 2010.
  • M. Aktan, A. Yurdakul and G. Dundar, "An Algorithm for the Design of Low-Power Hardware Efficient FIR Filters, " IEEE Transactions on CAS-I, vol. 55, no. 6, pp. 1536-1545, July 2008 .
  • G. Kabukcu and A. Yurdakul, "Low-cost solution to on-line color filter array demosaicking, " International Journal of Imaging Systems and Technology, vol. 17, no. 4, pp. 232-243, December 2007.
  • A. Yurdakul, “Multiplierless implementation of 2-D FIR filters”, Integration, the VLSI Journal Volume 38, Issue 4 , pp 597-613, April 2005.
  • A. Yurdakul and G. Dündar, "A Fast and Efficient Algorithm for the Multiplierless Realization of Linear DSP Transforms," IEE-Proceedings-Circuits Devices, and Systems, vol.149, pp.205-211, August 2002.
  • A. Yurdakul and G. Dündar, "Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions," Kluwer Journal of VLSI Signal Processing, vol.22, pp.163-172, September 1999
  • A. Yurdakul and G. Dündar, "Statistical Methods for the Estimation of Quantization Effects in FIR-Based Multirate Systems," IEEE Transactions on Signal Processing, vol.47, pp.1749-1753, June 1999.

 

Conferences

 

Türkçe Yayınlar

 

Edited Books, Journals and Proceedings

  • A. Yurdakul, B. Kurumahmut, G Kabukcu, “Generic Model for Application-Specific Processors on Reconfigurable Fabric,” in Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s, Vol. 63, 2010, ISBN: 978-90-481-9303-5
  • A. Yurdakul, Digital Design Experiments with Labview(R) and Xilinx-ISE(R), 244 pages, ISBN: 975-518-219-5, Boğaziçi University Press, February 2004.

Contact us

Department of Computer Engineering, Boğaziçi University,
34342 Bebek, Istanbul, Turkey

  • Phone: +90 212 359 45 23/24
  • Fax: +90 212 2872461
 

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