CmpE 584 Sp.Tp. Reconfigurable Computing 2020 Spring


Course Schedule: 


Course Program: 

This is an intemediate level to advanced level course on accelerated computing with Field Programming Gate Arrays (FPGAs). Its center is high level synthesis which enables accelerator design with an object oriented language such as C++. We will be using tools from Xilinx, which is one of the major vendors in FPGA business. By the end of the semester, each student will have completed the implementation of a hardware accelerator such as algorithmic trading, deep learning, cryptographic operations, Bitcoin mining or other perfomance-requiring algorithm. In this course we will study on the following topics:

  1. FPGAs: What are they? When should we use them? The rise of FPGAs in high performance computing
  2. High-level Synthesis (HLS) Basics: Input, Output, Data flow, Control flow, Scheduling, Resource Allocation. Design Space Exploration. Objectives. Constraints. Debug. Functional  testing. Co-Simulation.
  3. HLS at work - Data Types: Fixed point data types. Data structures. Loops: Pipelining, Parallelism, Unrolling, Bounds, Dependencies between iterations, Optimizing Loop Counter, Optimizing Loop Control, Nested LoopsInterfaces and Arrays: Conditional and unconditional I/O. Stream I/O. Array to memory mapping. Designing for throughput.
  4. System Integration – HW/SW interfaces. IP generation. Run-time tests and simulations
  5. Domain Specific Architectures: Application Acceleration. Dataflow Computing. Dataflow architectures. Partial Reconfiguration


D. Koch, F. Hannig, D. Ziener, FPGAs for Software Programmers, Springer, 2016


  • HWs and Coding Assignments: 40% (for each submission, late is penalized by 20% per day)
  • Attendance + Quizzes: 10% (no make up)
  • Project: 50% (for each of the following item, late is penalized by 100% per minute)
    • Project idea presentation: 5% (due date: Feb 24)
    • Project first progress presentation+demo: 15% (due date: March 23) – new date: April 13
    • Project second progress presentation+demo: 20% (due date: April 13) – new date: May 4
    • Final presentation+demo: 30% (due date: May 11) – new date: June 1
    • Project Report + Code Submission: 30% (due date: Final date)


Contact us

Department of Computer Engineering, Boğaziçi University,
34342 Bebek, Istanbul, Turkey

  • Phone: +90 212 359 45 23/24
  • Fax: +90 212 2872461

Connect with us

We're on Social Networks. Follow us & get in touch.